

Benedikt Bollig
I am a full-time researcher at Centre National de la Recherche Scientifique (CNRS) and affiliated with Laboratoire Spécification et Vérification, ENS Paris-Saclay, France. I am head of the VASCO team. My research interests are in the areas of automata theory and logic, with a focus on applications in synthesis and verification of concurrent and distributed systems.
News
September 22, 2020
New arXiv paper
The paper
Property-Directed Verification of Recurrent Neural Networks
(by the LeaRNNify team) is available on arXiv.
August 31, 2020
CONCUR'20 Best Paper Award
For our paper
Bounded Reachability Problems Are Decidable in FIFO Machines
(with Alain Finkel and Amrita Suresh), we received the best paper award at CONCUR'20.
August 02, 2020
GandALF'20 paper
Our paper
Synthesis in Presence of Dynamic Links
(with Béatrice Bérard, Patricia Bouyer, Matthias Függer, and Nathalie Sznajder) was accepted for presentation at GandALF'20.
March 08, 2020
LeaRNNify project
The project
LeaRNNify: New Challenges for Recurrent Neural Networks and Grammatical Inference
(Programme Procope 2020) with our partners Daniel Neider (MPI Kaiserslautern) and Martin Leucker (Universität Lübeck) has started.
September 06, 2018
CONCUR'18 Best Paper Award
For our paper
It Is Easy to Be Wise After the Event: Communicating Finite-State Machines Capture First-Order Logic with "Happened Before"
(with Marie Fortin and Paul Gastin), we received the best paper award at CONCUR'18.



June 17, 2019
Talk at Journées annuelles du GT Vérif
At the Journées annuelles du GT Vérif, I gave an invited presentation about our FoSSaCS'19 paper:
Identifiers in Registers - Describing Network Algorithms with Logic
January 20, 2019
Talk at CAALM 2019
At the CAALM workshop (Complexity, Algorithms, Automata and Logic Meet) in Chennai, India, I gave an invited presentation about our CONCUR'18 paper:
It Is Easy to Be Wise After the Event: Communicating Finite-State Machines Capture First-Order Logic with "Happened Before"
March 07, 2018
Talk in Verification Seminar at University of Oxford
I presented our paper
Communicating Finite-State Machines and Two-Variable Logic
in the Verification Seminar of the Department of Computer Science at the University of Oxford.
September 05, 2016
Invited Tutorial at Highlights'16
At Highlights 2016, I gave a tutorial on
Automata and Logics for Distributed Systems.
The tutorial covers several models of distributed systems in a unifying framework.
March 30, 2020
PC member of FSTTCS'20, GandALF'20, and ICTAC'20
I will serve on the Program Committees of FSTTCS'20 (14–19 December 2020, BITS Goa, India), GandALF'20 (21–23 September 2020, Brussels, Belgium), and ICTAC'20 (30 November - 4 December 2020, Macau S.A.R., China).
September 25, 2019
With C. Aiswarya and S. Akshay, I am organizing GALA 2019: Gems of Automata, Logic and Algebra. The workshop, which is co-located with FSTTCS 2019, takes place on December 14, 2019, at the Indian Institute of Technology Bombay.
July 19, 2018
Organizing MOVEP'18
I co-organized (with Peter Habermehl) the 13th Summer School on Modelling and Verification of Parallel Processes (MOVEP'18).
Journées GT Vérif
Join us at the Journées GT Vérif (17–19 November 2021), which takes place at LMF, ENS Paris-Saclay.
Imprint/Impressum:
Benedikt Bollig
ENS Paris-Saclay, LSV
4, avenue des Sciences
CS 30008
91192 Gif-sur-Yvette
France
Phone: +33 (0)1 81 87 54 32